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Difference between revisions of "EclipseLink/Examples/JPA/Simulation"

m (Simulation JPA Application Example)
m (Simulation JPA Application Example)
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*This sumulation will serve as a ''near real world'' enterprise application that showcases utilizing JPA as the persistence or integration layer - specifically using EclipseLink JPA as the provider.
 
*This sumulation will serve as a ''near real world'' enterprise application that showcases utilizing JPA as the persistence or integration layer - specifically using EclipseLink JPA as the provider.
 
*This enterprise application will offer the services of a simulated connection machine ''(Ref: Thinking Machines CM-2)'' symbolic vector processor.
 
*This enterprise application will offer the services of a simulated connection machine ''(Ref: Thinking Machines CM-2)'' symbolic vector processor.
 +
**Why are we choosing an older architecture to simulate?
 +
***A) The architecture is very clean and even though it is very large - is simple enough to implement.
 +
***A) The design is proven and static - as it has been superceeded by more powerfull designs).
 
===Goals===
 
===Goals===
 
*We would like to explore the following limits of the JPA provider and hosting application server.
 
*We would like to explore the following limits of the JPA provider and hosting application server.
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====Processor Architecture====
 
====Processor Architecture====
 
*Each CM-2 processor is composed of up to '''64k (65536)''' 1-bit processors arranged in a 12-dimensional hypercube.
 
*Each CM-2 processor is composed of up to '''64k (65536)''' 1-bit processors arranged in a 12-dimensional hypercube.
**There are '''16''' 1-bit processors per chip.
+
**There are '''16''' 1-bit processors per chip along with '''1''' routing processor per chip.
***There are '''32''' processor chips per backplane board
+
***There are '''32''' cpu chips and '''32''' ram chips per backplane board
 
****There are '''16''' boards per quadrant
 
****There are '''16''' boards per quadrant
 
*****There are '''8''' quadrands to a CM-2
 
*****There are '''8''' quadrands to a CM-2
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====Hierarchy====
 
====Hierarchy====
*hypercube
+
*Hypercube (quadrants(1:M), input, output)
**
+
*Quadrant (boards(1:M), hypercube(1:1))
 +
*Board (processorChips(1:M), ramChips(1:M))
 +
*''Chip(A)''
 +
**ProcessorChip (processors (1:M), router (1:1))
 +
**MemoryChip
 +
*''Processor(A)''
 +
**VectorProcessor(alu)
 +
**RouterProcessor (routers(1:M))
 +
 
 
==Design==
 
==Design==
 
==Implementation==
 
==Implementation==

Revision as of 12:03, 31 August 2009

Simulation JPA Application Example

Purpose

  • This sumulation will serve as a near real world enterprise application that showcases utilizing JPA as the persistence or integration layer - specifically using EclipseLink JPA as the provider.
  • This enterprise application will offer the services of a simulated connection machine (Ref: Thinking Machines CM-2) symbolic vector processor.
    • Why are we choosing an older architecture to simulate?
      • A) The architecture is very clean and even though it is very large - is simple enough to implement.
      • A) The design is proven and static - as it has been superceeded by more powerfull designs).

Goals

  • We would like to explore the following limits of the JPA provider and hosting application server.
    • Performance and Volumetrics: We require 65536 processor objects.

Infrastructure

  • OS: Windows XP or Vista 32/64 bit
  • Database: Oracle 11gR1
  • JPA provider: EclipseLink 1.2
  • JDK: Sun 1.6.0_14

Analysis

Data Model

Processor Architecture

  • Each CM-2 processor is composed of up to 64k (65536) 1-bit processors arranged in a 12-dimensional hypercube.
    • There are 16 1-bit processors per chip along with 1 routing processor per chip.
      • There are 32 cpu chips and 32 ram chips per backplane board
        • There are 16 boards per quadrant
          • There are 8 quadrands to a CM-2
    • We therefore have (2^4=16) x (2^5=32) x (2^4=16) x (2^3=8) = 2^16 = 65536 possible processors in a fully configured system.

Hierarchy

  • Hypercube (quadrants(1:M), input, output)
  • Quadrant (boards(1:M), hypercube(1:1))
  • Board (processorChips(1:M), ramChips(1:M))
  • Chip(A)
    • ProcessorChip (processors (1:M), router (1:1))
    • MemoryChip
  • Processor(A)
    • VectorProcessor(alu)
    • RouterProcessor (routers(1:M))

Design

Implementation

Schema Model

Testing

Appendices

References

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